The invention relates to a method for fabricating a semiconductor device. More specifically, the invention relates to selective etching using a hard mask and a method for forming an isolation structure of a memory device using selective etching.
With decreasing design rules and increasing levels of integration for semiconductor devices, there have been attempts to make patterns finer by reducing the loss of photoresists. For example, there have been used etching masks made of a material having superior etching resistance and a high hardness, e.g., silicon nitride (Si3N4) or silicon oxynitride (SiON), as compared to photoresist etching masks. That is to say, in etching processes, there have been employed hard masks made of materials having a higher etching resistance than that of photoresist mask materials.
With the demand for an increase in etching rates and for fine linewidths of photoresist patterns, there have been suggestions to introduce hard masks having a multilayer structure including different insulating layers. In particular, to simplify the etching process of devices with transistors having a complicated structure, such as NAND flash memory devices, multilayer hard masks are used to etch a trench for isolating the device in each cell.
FIGS. 1 to 3 are cross-sectional views schematically illustrating a selective etching process using conventional hard masks.
Referring to FIGS. 1 to 3, non-volatile devices, such as flash memory devices, include a transistor having a structure in which a control gate is laminated on a charge storage layer or a floating gate. A device isolation structure to isolate devices in each cell is formed in accordance with a first pattern of the charge storage layer. That is, a selective etching process to first pattern the charge storage layer, and a trench etching process on the semiconductor substrate exposed during the first patterning are sequentially performed, thereby simplifying the process. As such, in an attempt to selectively etch multilayer etching targets, a multilayer hard mask structure is introduced.
More specifically, as shown in FIG. 1, a tunnel dielectric layer 12 including an oxide layer is formed on a semiconductor substrate 11. A charge storage layer 13 (e.g., a conductive polysilicon layer) is formed on the tunnel dielectric layer 12. A hard mask 17 used for selectively etching the charge storage layer 13 is formed on the charge storage layer 13. A process for forming the hard mask 17 will be illustrated in more detail. First, a pad layer 14 is formed on the charge storage layer 13. The pad layer 14 acts as a polishing stop point while a device isolation layer is planarized by chemical mechanical polishing (CMP). The pad layer 14 preferably includes a silicon nitride layer.
The hard mask 17 is a multilayer structure formed on the pad layer 14. The hard mask 17 may have a multilayered structure in which a plurality of insulating layers such as a silicon oxide layer 15 and a silicon oxynitride layer 16, each having a thickness of about 800 Å, are sequentially laminated. Then, a photoresist pattern 18 used for selective etching is formed on the resulting structure to a thickness of about 1,700 Å.
As shown in FIG. 1, the photoresist pattern 18 is used as an etching mask upon for selective etching to pattern the multilayered hard mask 17 or to firstly pattern the charge storage layer 13. As shown in FIG. 2, the hard mask 17 is used as an etching mask upon selectively etching a region where the semiconductor substrate 11 is exposed through the first pattern of the charge storage layer 13.
As shown in FIG. 3, the multilayered hard mask 17 is used as an etching mask upon selective etching to form a trench 19 by etching the exposed semiconductor substrate 11. Accordingly, the hard mask 17 includes a multilayer of insulating layers with a sufficient thickness having different etching selectivities so that the hard mask 17 can resist the etching step for forming a trench 19. There is a risk that the underlying silicon oxide layer 15 is partially lost upon etching. Accordingly, taking into consideration the etching residue, the thickness of the underlying silicon oxide layer 15 must be sufficiently secured.
In order to desirably function as an etching mask upon etching to pattern the multilayered thick hard mask 17, the photoresist pattern 18 is formed to a sufficiently large thickness while taking into consideration damage caused by etching. In a case where the photoresist pattern 18 is formed to an excessive thickness, it becomes difficult to finely expose and develop the photoresist pattern 18. In addition, the line-widths of the trench 19 and the charge storage layer 13 cannot be adjusted to a desired level. As a result, a reduction in process margin occurs. Furthermore, each insulating layer constituting the multilayered hard mask 17 necessarily involves deposition and etching processes, thus complicating the overall process.
Accordingly, to simplify the overall process and improve the fine pattern of the photoresist, there is a need to develop a method capable of reducing the total thickness of the etching mask including the hard mask 17 and the photoresist pattern 18.